ASPENLOGIC® Project Portfolio

Project
Custom 1024 Channel DAC Controller

Designed, implemented and simulated the VHDL design for a custom 1024 channel DAC controller (via 256 DACs) that required broadcast capability in addition to programmable FIFO read access for maximum throughput to the total array of DACs. The SPI bridge was developed to permit parallel access in groups of 64 channels as needed by the system processor.


Custom DAC, SPI, VHDL
High Speed DDS to JESD204B DAC Interface

Accepted the task of reviewing and locating bugs in an overdue digital synthesizer design using a 4-lane JESD204B interface comprising a Xilinx DDS core, Xilinx JESD204B TX core (hosted in an Artix XC7A200T-1FFG1156I FPGA), a TI LMK04828 Clock Generator and TI DAC39j84 Quad, 2.8-GSPS Digital to Analog Converter. Re-wrote the startup state machine for initializing the system (not as easy as it sounds) and provided analysis of the entire design for management.


DAC, DAC39j84, DDS, JESD204B, LMK04828, XC7A200T
Multi-FPGA Embedded System Debug

The Customer was struggling with a mission critical, embedded design, hosted on a main FPGA board Microblaze soft processor design interfaced with eight daughter cards. A TCP/IP stack provided connectivity to the PC with data collected from eight infrared sensors on each of the daughter cards. The traditional SDK based debugging had run out of steam as months had passed with no viable leads on the cause of a random operational bug. Utilizing Xilinx® Chipscope™, I was able to locate a randomly pulsing signal used in an asyncronous FSM reset. Driving to root cause, I examined the board schematic and discovered a level translator employed to supply a 'board present signal' driving an FPGA pullup input. Forbidden by the translator's device datasheet, the output driver could not overcome the weak pullup in the FPGA. The original (two) FPGA HDL authors, the software engineer and the board design engineer had completely missed the subtle bug caused by this connection. Also, upgraded the socket connection from LwIP to the commercial Treck stack. Implemented FPGA source code control using Subversion and took the design through eight major releases.


Chipscope, Debug, FPGA, LwIP, Microblaze, TCP/IP, Verilog, VoSPI
1000Base-X GigE Fiber Link Project Rescue

Rescued customer and prevented their loss of a major government contract by quickly assessing the defects in the implementation of their Gigabit Ethernet (1000Base-X) fiber optic link. Proposed and delivered a start-from-scratch implementation of their Data Capture System. Participated in daily stand up meetings while also managing junior engineer, coding new VHDL, debugging multiple PCBs with Virtex-6 LX240T devices on each, interfacing with software development, and supporting government site testing of new hardware, firmware and software. Customer met its milestone and successfully collected necessary data using the new ASPENLOGIC® developed system.


1000Base-X, Fiber Optics, FPGA, LX240T, VHDL, Virtex-6
Custom Interface to High Frame Rate Camera

Developed an 80 MHz Cameralink dual medium interface for the Xenics Cheetah-640CL which was the world's fastest IR camera. This project also required the design of VHDL interface code for talking with peripherals connected to a TB-6V-LX550T-PCIEXP. It communicated using the Xilinx Aurora protocol over two sets of four 3.125 Gbps fiber optic links to Virtex-6 SX475T and SX315T populated XMC cards. Co-designed the architecture and VHDL implementation strategy for the entire system.


Aurora, Cameralink, Fiber Optics, High Speed Serial, LX550T, SX315T, SX475T, VHDL, Virtex-6
Marketed and Sold TED FPGA Development Boards

Developed website pages and marketing content to sell Tokyo Electron Device development boards directly to world-wide customers over the internet. Provided phone & email technical support for all products as requested. Delivered outstanding results including the most sales of high end Virtex 6 LX550T development boards in TED history to a single UK customer. Customers appreciated the one stop shop approach.


Sales, Tokyo Electron Device, Virtex 6
Medical Device FPGA Development Process

Wrote a process for developing project specific FPGA development processes (to meet ISO standards) for a major medical products company.


FPGA
Augmented OVM Test with System Verilog Assertions

A new customer needed ASPENLOGIC® to review an existing, well tested Verilog FPGA design (code + specification documents) to determine if adding SystemVerilog (IEEE Std 1800) assertions was necessary. After adding nearly 40 assertions the constrained random OVM simulation showed errors on a number of the assertions.


IEEE Std 1800, SystemVerilog Assertions
Short Notice Completion of Critical FPGA Development Task

On several hours notice ASPENLOGIC® appeared at a customer site to takeover a task from another engineer leaving for a death in the family. This critical task had to be completed in order to ensure a deadline was met just a month away. After a 2-hour task hand off meeting, ASPENLOGIC® completed the VHDL design and coding task and delivered the code for integration without supervision of the departing engineer.


Crisis Intervention
Integrated Xilinx IP to Form Custom Multi-Channel Fiber Optic Comm System

ASPENLOGIC® integrated three pieces of Xilinx IP to form a stunning data capture and processing engine for its client. 2.5 Gb/s Fiber optic connections between custom, multi-channel ADC/DAC boards and a COTS Avnet evaluation board with a Virtex-5™ SX95T device operating at 250 Mhz delivered high bandwidth connectivity to the proprietary processing engine. The VHDL was designed to replicate a variable number of processing modules and automatically connect them to a variable number of bidirectional Aurora protocol links utilizing SFP optical fiber transceivers. Host software configured each board and received diagnostic information through a register interface accessed via PCI Express.


Aurora Serial Link, Fiber Optics, PCIe, Serial Link, SFP, VHDL, Virtex-5
Embedded Development PCores

As a Processor IP developer I created new pcores delivered with the Xilinx Embedded Development Kit. Responsible for design, implementation and hardware testing of OPB to PLBv46 bridges, XPS_IIC upgrades, and the PPC 440 DMA Engine to PCI Express Integrated Endpoint bridge.


Microblaze, PCIe Endpoint, PCORE, XPS_IIC
Sofware Defined Radio TX&RX Path FPGA Logic

Drove architecture and implementation of digital logic in the transmit and receive paths of a software defined radio (SDR) for a proprietary continuous phase modulation waveform. Worked w/ Linux driver development specialist to define interface to core logic via a Quicklogic 5064 PCI bus interface IC. Verified, designed and implemented FPGA logic in VHDL for Xilinx Virtex™-4 (170+ Mhz) and Virtex-II devices.


Continuous Phase Modulation, Quicklogic 5064, SDR, Software Defined Radio, VHDL, Virtex-4, Virtex-II
Custom Bus Implementation and Analysis

Designed custom bus implementation to insert master controlled prioritization of data accesses between 16-slave ASICs using Actel ProASICPLUS plus parts.


Actel, FPGA, ProASICPLUS
Verilog Test Plan and Testbench

Delivered verilog testplan and testbench for Actel FPGA design. Went beyond scope of original test plan and implemented system level verification that ultimately proved the original design concept could not work thus saving design teams months of difficult board level debug in the lab.


Actel, FPGA, Simulation, Verification, Verilog
Expert Patent Dispute Consulting

Delivered expert consulting to attorneys on patent dispute. Provided declaration regarding simulation of DRAM circuits using HSPICE. Case settled.


DRAM, Expert Patent Consulting, HSPICE
Debugged Multi-Million gate SOC ASIC to Save Project From Failure

Debugged intractable problem in the gate level implementation of a multi-million gate SOC which the designers spent three months trying to find. I Discovered a flaw in the timing analysis that allowed the design to pass static timing analysis (STA) yet fail in silicon. After examining the pattern of instruction fetch address generation failures, I hypothesized and proved the conjecture that a single hold time violation on one bit of a critical state machine logic path was to blame. Customer verified my suggested modification through E-Beam modification of actual silicon.


ASIC, Debug, SOC, STA
Programmable Hardware Test Engine

Worked the design of a special purpose, programmable hardware test engine which utilized three ep20k300efi672 Altera Apex20ke FPGAs. Captured the design in VHDL and synthesized with Leonardo Spectrum and Quartus 2.2 software. Managed the design hierarchy to optimize the re-utilization of logic between the three devices to improve time-to-market. Delivered a synthesizable SDRAM controller, in two weeks, for use between a proprietary message protocol bus and a Micron SDRAM.


Altera, APEX20KE, FPGA, Leonardo Spectrum, Quartus, SDRAM
Network Process SPI-3 Gasket

Delivered Xilinx Spartan™ IIE FPGA to connect the Vitesse (Sitera) IQ2x000 network processor to a custom SPI-3 interface requiring link and phy interfaces for the receive path. Extensive testing yielded a design without defects that was delivered on-time and months before the customer (Sun Microsystems) needed the device for in-system integration.


IQ2X000, Network Processor, Sitera, Spartan IIe, SPI-3, Vitesse
Focus Bus to CrossStream Bus Gasket

Delivered Xilinx Virtex™ FPGA to connect Vitesse IQ2000 network processor and VSC870/VSC880 components by translating between the Focus bus and CrossStream bus protocols of the two devices.


CrossStream Bus, Focus Bus, IQ2000, Virtex, Vitesse, VSC870, VSC880
Optical Correlator Controller FPGA Debug

Debugged 33 Mhz PCI card containing PLX PCI controller, and Xilinx 4028XL FPGA designed to communicate with a custom silicon optical correlator.


Optical Correlator, PCI, PLX, XC4028XL
Analog SLM PCI Card Debug

Delivered crisis intervention support on a late project for a PCI card design. The system did not send correctly formatted data to the analog spatial light modulator (SLM). Re-architecting the design yielded a functional platform for testing of the SLM.


Crisis Intervention, Debug, PCI, SLM
Expert Consulting

Provided expert consulting to attorneys on an ASIC design contract dispute. Reviewed materials and coached staff on structure of ASICs and their design methodology.


Expert Witness
Fibre Channel FPGA

Investigated and began preliminary design of synthesizable models for FC-1 and FC-2 levels of a a custom PCI Fibre Channel Interface card intended for Silicon Graphics (SGI). Wrote C program to generate gate level structural VHDL netlists to compute arbitrary polynomial, parallel CRC operations.


C, Fiber Channel, Parallel CRC
Displaytech FLC SLM Controller

Developed several high speed (65 Mhz) FPGA based, time-sequential color framebuffer controllers for Displaytech Inc.’s ferroelectric liquid crystal (FLC), time sequential color, spatial light modulators. Controllers interfaced to VRAM and SDRAM memory. FPGA designs done with VHDL, Exemplar Logic Leonardo Synthesis software, and Xilinx M1 P&R software. Continued development for customer on next generation FLC Display controller(s).


Exemplar Leonardo, FLC, Frame Buffer, SDRAM, SLM, VRAM, Xilinx M1
Short Notice Engineering Replacement

Stepped in on few days notice to replace an engineer at client site. Found and fixed over 20 bugs in engineer’s ECC softcore controller design -- several were show stoppers. Brought design back to Colorado to complete simulation against test plan I developed. Work on other client projects required rapid acquisition of knowledge about error control coding mathematics to complete modifications to Perl scripts, which programmed the creation of schematics in Design Architect.


Debug, Design Architect, ECC, Error Control Coding, Perl
ASIC Design Crisis Intervention

Performed scheduling and management of a two-week project to design and simulate control logic for a client with a hard, ASIC, fab deadline in order to replace uncompleted work by another vendor. Extracted design requirements from customer specification and developed test plan to guide verification effort. Supervised partners in VHDL design and simulation to meet goals and performed design synthesis using Veribest Inc.'s synthesis software.


Synthesis, Veribest, VHDL
Esperan VHDL Training

Delivered hundreds of hours worth of VHDL training courses for Esperan Ltd., an English VHDL training company.


training, VHDL
3D Graphics ASIC Consulting

Consulted to Ball Corporation's Real Time Imaging unit on a graphics pipeline ASIC chip set. Established a design methodology which made it possible for the design team to create the chip set in record time. It also lead to a reduction in the size of the largest device by 30% over the previous design. Also designed hardware, directed other consultants in development of floating point hardware, and trained team members in VHDL and Mentor Graphics Autologic synthesis tools.


3D Graphics, ASIC, Floating Point, VHDL
GE FANUC ASIC Consulting

Consulted to GE Fanuc Automation in their ASIC design efforts, and trained them in the Mentor Graphics Top-Down design processes.


ASIC, Top-down Design, training
AG Comm ASIC Consulting

Consulted to AG Communications Systems in their ASIC design efforts, and trained them in the Mentor Graphics Top-Down design processes. Wrote data pattern generator for testing T1 frame sync operation


ASIC, T1, Top-down Design, training
Intel ASIC Consulting

Consulted on ASIC designs for an Intel super-computer project requiring a sophisticated, multi-cpu reset initialization controller.


ASIC, Intel, Reset Logic, VHDL
VHDL Seminar

Developed and presented seminar at the 1992 VHDL International Users Forum entitled, “VHDL vis-a-vis Top-Down Design”.


VHDL
Custom VHDL Training

Created and delivered custom, four-day, VHDL and synthesis training course to Siemens Gammasonics and AT&T (Lucent Technologies).


training, VHDL