The Customer was struggling with a mission critical, embedded design, hosted on a main FPGA board Microblaze soft processor design interfaced with eight daughter cards. A TCP/IP stack provided connectivity to the PC with data collected from eight infrared sensors on each of the daughter cards. The traditional SDK based debugging had run out of steam as months had passed with no viable leads on the cause of a random operational bug. Utilizing Xilinx® Chipscope™, I was able to locate a randomly pulsing signal used in an asyncronous FSM reset.
Rescued customer and prevented their loss of a major government contract by quickly assessing the defects in the implementation of their Gigabit Ethernet (1000Base-X) fiber optic link. Proposed and delivered a start-from-scratch implementation of their Data Capture System. Participated in daily stand up meetings while also managing junior engineer, coding new VHDL, debugging multiple PCBs with Virtex-6 LX240T devices on each, interfacing with software development, and supporting government site testing of new hardware, firmware and software.
Wrote a process for developing project specific FPGA development processes (to meet ISO standards) for a major medical products company.
Designed custom bus implementation to insert master controlled prioritization of data accesses between 16-slave ASICs using Actel ProASICPLUS plus parts.
Delivered verilog testplan and testbench for Actel FPGA design. Went beyond scope of original test plan and implemented system level verification that ultimately proved the original design concept could not work thus saving design teams months of difficult board level debug in the lab.
Worked the design of a special purpose, programmable hardware test engine which utilized three ep20k300efi672 Altera Apex20ke FPGAs. Captured the design in VHDL and synthesized with Leonardo Spectrum and Quartus 2.2 software. Managed the design hierarchy to optimize the re-utilization of logic between the three devices to improve time-to-market. Delivered a synthesizable SDRAM controller, in two weeks, for use between a proprietary message protocol bus and a Micron SDRAM.
Who knew that transistors would have such a transformative power over our daily lives? We carry billions of them around in our pocket, on our wrist, in our computers. They are ubiquitous but also invisible.
I have rescued a few designs during my 25+ years at the helm of Aspen Logic's FPGA/ASIC contracting business. Reasons abound for the causes of the failures but there are three areas that need consistent focus:
- Designers give little up front thought to logic reset which leads to insidious, hard to find bugs
- Management typically assigns a cost of $0 to bugs because FPGA devices are re-programmable so no time is allocated in the schedule for squishing them
- Lack of a road map for features and fixes which makes decision making on large design efforts difficult
The typical article on metastability in the flip flop synchronizer (used for clock domain crossing) delivers volumes about the MTBF ("Mean Time Between Failure") equation but falls short when explaining practical ways to manage the failure rate.