Tim Davis's blog

Bugs? Not in my schedule please.

I have rescued a few designs during my 25+ years at the helm of Aspen Logic's FPGA/ASIC contracting business. Reasons abound for the causes of the failures but there are three areas that need consistent focus:

  1. Designers give little up front thought to logic reset which leads to insidious, hard to find bugs
  2. Management typically assigns a cost of $0 to bugs because FPGA devices are re-programmable so no time is allocated in the schedule for squishing them
  3. Lack of a road map for features and fixes which makes decision making on large design efforts difficult

Verifying Validation and Validating Verification

People (I guess we classify engineers as people) have always talked about verification and the "testing" of a piece of hardware to see if it works as the "same thing". Unfortunately for us there is a movement within international standards bodies (dating back centuries) to have us believe that there are really two types of testing: verification and validation.

Is your head spinning?