Sometimes, achieving timing closure on an FPGA design becomes a hugely frustrating exercise to cross the gap of that last nanosecond.
Tim Davis's blog
Who knew that transistors would have such a transformative power over our daily lives? We carry billions of them around in our pocket, on our wrist, in our computers. They are ubiquitous but also invisible.
I have rescued a few designs during my 25+ years at the helm of Aspen Logic's FPGA/ASIC contracting business. Reasons abound for the causes of the failures but there are three areas that need consistent focus:
- Designers give little up front thought to logic reset which leads to insidious, hard to find bugs
- Management typically assigns a cost of $0 to bugs because FPGA devices are re-programmable so no time is allocated in the schedule for squishing them
- Lack of a road map for features and fixes which makes decision making on large design efforts difficult