The Knob Setting Insanity of FPGA Timing Closure
Sometimes, achieving timing closure on an FPGA design becomes a hugely frustrating exercise to cross the gap of that last nanosecond.
From the beginning, you took all necessary steps to ensure the highest quality code, tuning it according to the FPGA vendor's coding style guide to achieve optimum performance. Right?
Except, of course, when your design is not an FPGA, but an ASIC that you are prototyping. Then, all bets are off because you do not want to follow an FPGA style guide and you most definitely do not want to modify your HDL code. DUH!
Except, of course, when a portion of your design is 3rd party IP, you do not have the source code and are never going to get it. You have to hope the designers followed the style guide for you.
Except, of course, when the design has been through rigorous verification and HDL changes are off limits except for the most egregious bugs. (Who cares if does not meeting timing! It works perfectly in simulation.)
That leaves you with the option to improve your design's performance by twisting knobs this way and that. By "knobs" I mean all those tool configuration parameters that subtly adjust the heuristics employed by the vendor to solve the gnarly timing closure problem you threw at it.
How many synthesis, map, place and route parameter "knobs" do the vendor tools present for you to adjust? The number of possible settings is enough to drive you insane. The cure begins with acknowledging that you just do not understand what all those tool parameter knobs do. (And maybe, just maybe, your FAE should acknowledge that, too.)
It is time to stop manually running build after build, tweaking this red knob or that blue one, trying to judge which way the needle is moving from random experimentation and headache inducing dives into dense timing reports.
Why not give all that nasty work, the heavy lifting and sweating over those knobs and reports, to the machines?
The engineers at Plunify did the research and from it crafted a smart tool called InTime that utilizes machine learning algorithms to make your FPGA design or ASIC prototype faster by intelligently adjusting those knobs in a methodical manner. The logic of this approach is inescapable and most importantly, it saves you from going insane.
What did you think after giving it a try?