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The Customer was struggling with a mission critical, embedded design, hosted on a Microblaze soft processor on a main board with eight daughter cards. A TCP/IP stack provided connectivity to the PC with data collected from eight infrared sensors on each of the daughter cards. The traditional SDK based debugging had run out of steam as months had passed with no viable leads on the cause of a random operational bug. Utilizing Xilinx Chipscope, I was able to locate a randomly pulsing signal used in a FSM reset. Driving to root cause, I examined the board schematic and discovered a level translator employed to supply a 'board present signal' driving an FPGA pullup input. Forbidden by the translator's device datasheet, the output driver could not overcome the weak pullup in the FPGA. The original (two) FPGA HDL authors, the software engineer and the board design engineer had completely missed the subtle bug caused by this connection. Also, upgraded the socket connection from LwIP to the commercial Treck stack.
Rescued customer and prevented their loss of a major government contract by quickly assessing the defects in the implementation of their Gigabit Ethernet (1000Base-X) fiber optic link and proposing a start-from-scratch implementation of their Data Capture System. Participated in daily stand up meetings while also managing junior engineer, coding new VHDL, debugging multiple PCBs with Virtex-6 LX240T devices on each, interfacing with software development, and supporting government site testing of new hardware, firmware and software. Customer met its milestone and sucessfully collected necessary data using the new Aspen Logic system. Customer consensus was: "You walk on water!"
Design, implemented and simulated the VHDL design for a custom 1024 channel DAC controller (via 256 DACs) that required broadcast capability in addition to programmable FIFO read access for maximum throughput to the total array of DACs. The SPI bridge was developed to permit parallel access in groups of 64 channels as needed by the system processor.
Developed an 80 MHz Cameralink dual medium interface for the Xenics Cheetah-640CL which is the world's fastest IR camera. This project also required the design of VHDL interface code for talking with peripherals connected to a TB-6V-LX550T-PCIEXP which communicated using the Xilinx Aurora protocol over two sets of four 3.125 Gbps fiber optic links to Virtex-6 SX475T and SX315T populated XMC cards. Co-designed the architecture and VHDL implementation strategy for the entire system.
Sold Tokyo Electron Device development boards and provided phone & email technical support for all products as requested. Delivered outstanding results including the most sales of high end Virtex 6 LX550T development boards in TED history to a single UK customer. Customers appreciated the one stop shop approach.
Wrote a process for developing project specific FPGA development processes (to meet ISO standards) for a major medical products company.
A new customer needed ASPENLOGIC® to review an existing, well tested Verilog FPGA design (code + specification documents) to determine if adding SystemVerilog (IEEE Std 1800) assertions was necessary. After adding nearly 40 assertions the constrained random OVM simulation showed errors on a number of the assertions.
On several hours notice ASPENLOGIC® appeared at a customer site to takeover a task from another engineer leaving for a death in the family. This critical task had to be completed in order to ensure a deadline was met just a month away. After a 2-hour task hand off meeting, ASPENLOGIC® completed the VHDL design and coding task and delivered the code for integration without supervision of the departing engineer.
ASPENLOGIC® integrated three pieces of Xilinx IP to form a stunning data capture and processing engine for its client. 2.5 Gb/s Fiber optic connections between custom, multi-channel ADC/DAC boards and a COTS Avnet evaluation board with a Virtex-5™ SX95T device operating at 250 Mhz delivered high bandwidth connectivity to the proprietary processing engine. The VHDL was designed to replicate a variable number of processing modules and automatically connect them to a variable number of bidirectional Aurora protocol links utilizing SFP optical fiber tranceivers. Host software configured each board and received diagnostic information through a register interface accessed via PCI Express.
As a Processor IP developer I created new pcores delivered with the Xilinx Embedded Development Kit. Responsible for design, implementation and hardware testing of OPB to PLBv46 bridges, XPS_IIC upgrades, and the PPC 440 DMA Engine to PCI Express Integrated Endpoint bridge.
Drove architecture and implementation of digital logic in the transmit and receive paths of a software defined radio for proprietary continous phase modulation waveform. Worked w/ Linux driver development specialist to define interface to core logic via a Quicklogic 5064 PCI bus interface IC. Verified, designed and implemented FPGA logic in VHDL for Xilinx Virtex™-4 (170+ Mhz) and Virtex-II devices.
Designed custom bus implementation to insert master controlled prioritization of data accesses between 16-slave asics using Actel ProASICPLUS plus parts.
Delivered verilog testplan and testbench for Actel FPGA design. Went beyond scope of original test plan and implemented system level verification that ultimately proved the original design concept could not work thus saving design teams months of difficult board level debug in the lab.
Delivered expert consulting to attorney’s on patent dispute. Provided declaration regarding simulation of DRAM circuits using HSPICE. Case settled.
Debugged intractable problem in the gate level implementation of a multi-million gate SOC which the designers spent months trying to find. I Discovered a flaw in the timing analysis that allowed the design to pass static timing analysis (STA) yet fail in silicon. After examing the pattern of instruction fetch address generation failures, I hypothesized and proved the conjecture that a single hold time violation on one bit of a critical state machine logic path was to blame.
Worked the design of a special purpose, programmable hardware test engine which utilized three ep20k300efi672 Altera Apex20ke FPGAs. Captured the design in VHDL and synthesized with Leonardo Spectrum and Quartus 2.2 software. Managed the design hierarchy to optimize the re-utilization of logic between the three devices to improve time-to-market. Delivered a synthesizable SDRAM controller, in two weeks, for use between a proprietary message protocol bus and a Micron SDRAM.
Delivered Xilinx Spartan™ IIE FPGA to connect the Vitesse (Sitera) IQ2x000 network processor to a custom SPI-3 interface requiring link and phy interfaces for the receive path. Extensive testing yielded a design without defects that was delivered on-time and months before the customer needed the device for in system integration.
Delivered Xilinx Virtex™ FPGA to connect Vitesse IQ2000 network processor and VSC870/VSC880 components by translating between the Focus bus and Crosstream bus protocols of the two devices.
Delivered crisis intervention support on a late project for a PCI card design. The system did not send correctly formatted data to the analog spatial light modulator (SLM). Re-architecting the design yielded a functional platform for testing of the SLM.
Provided expert consulting to attorneys on an ASIC design contract dispute. Reviewed materials and coached staff on structure of ASICs and their design methodology.