The typical article on metastability in the flip flop synchronizer
(used for clock domain crossing) delivers volumes about the MTBF ("Mean
Time Between Failure") equation but falls short when explaining
practical ways to manage the failure rate. This article reviews synchronizer MTBF and encourages the logic designer implementing synchronizers to employ physical constraints to ensure the design minimizes failure rate. It finishes with an example synchronizer implemented in VHDL w/ Xilinx constraints.