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Debugged 33 Mhz PCI card containing PLX PCI controller, and Xilinx 4028XL FPGA designed to communicate with a custom silicon optical correlator.
Investigated and began preliminary design of synthesizable models for FC-1 and FC-2 levels of a a custom PCI Fibre Channel Interface card intended for Silicon Graphics (SGI). Wrote C program to generate gate level structural VHDL netlists to compute arbitrary polynomial, parallel CRC operations.
Developed several high speed (65 Mhz) FPGA based, time-sequential color framebuffer controllers for Displaytech Inc.’s ferro electric liquid crystal (FLC), time sequential color, spatial light modulators. Controllers interfaced to VRAM and SDRAM memory. FPGA designs done with VHDL, Exemplar Logic Leonardo Synthesis software, and Xilinx M1 P&R software. Continued development for customer on next generation FLC Display controller(s).
Stepped in on few days notice to replace an engineer at client site. Found and fixed over 20 bugs in engineer’s ECC softcore controller design -- several were show stoppers. Brought design back to Colorado to complete simulation against test plan I developed. Work on other client projects required rapid acquisition of knowledge about error control coding mathematics to complete modifications to Perl scripts, which programmed the creation of schematics in Design Architect.
Delivered hundreds of hours worth of VHDL training courses for Esperan Ltd., an English VHDL training company.
Performed scheduling and management of a two-week project to design and simulate control logic for a client with a hard fab deadline in order to replace uncompleted work by another vendor. Extracted design requirments from customer specification and developed test plan to guide verification effort. Supervised partners in VHDL design and simulation to meet goals and performed design synthesis using Veribest Inc.’s synthesis software.
Consulted to Ball Corporation’s Real Time Imaging unit on a graphics pipeline ASIC chip set. Established a design methodology which made it possible for the design team to create the chip set in record time. It also lead to a reduction in the size of the largest device by 30% over the previous design. Also designed hardware, directed other consultants in development of floating point hardware, and trained team members in VHDL and Mentor Graphics tools.
Consulted to GE Fanuc Automation in their ASIC design efforts, and trained them in the Mentor Graphics Top-Down design processes.
Consulted to AG Communications Systems in their ASIC design efforts, and trained them in the Mentor Graphics Top-Down design processes. Wrote data pattern generator for testing T1 frame sync operation.
Consulted on ASIC designs for an Intel super-computer project requiring a sophisticated, multi-cpu reset initialization controller.
Developed and presented seminar at the 1992 VHDL International Users Forum entitled, “VHDL vis-a-vis Top-Down Design”.
Created and delivered custom, four-day, VHDL and synthesis training course to Siemens Gammasonics and AT&T (Lucent Technologies).