ASPEN LOGIC Project Portfolio

Took the responsibility for developing the system architecture for a custom 802.1Q bridge with customized 10GBASE-KR links operating with proprietary protocols to/from external ASICs. Wrote hardware design documentation and software interface documents including block diagrams and timing diagrams using MS Visio. Led technical interchange meetings with my customer’s customer to uncover and understand unstated FPGA requirements. Coded a highly programmable Time Division Multiplexing (TDM) scheduling back end with weighted fair queuing (WFQ), HDLC encoding, frame buffering, realignment engine and register interface in SystemVerilog. Coordinated verification with UVM development team. Operated remotely (COVID-19) for entire project and for a significant stretch without the FPGA lead who was out on paternity leave.

Accepted the task of reviewing and locating bugs for defense contractor in an overdue digital synthesizer design using a 4-lane JESD204B interface comprising a Xilinx DDS core, Xilinx JESD204B TX core (hosted in an Artix XC7A200T-1FFG1156I FPGA), a TI LMK04828 Clock Generator and TI DAC39j84 Quad, 2.8-GSPS Digital to Analog Converter. Re-wrote the startup state machine for initializing the system (not as easy as it sounds) and provided analysis of the entire design for management.

Rescued customer and prevented its loss of a major government contract by quickly assessing the defects in the implementation of its Gigabit Ethernet (1000Base-X) fiber optic link and proposing a start-from-scratch implementation of its Data Capture System. Participated in daily stand up meetings while also managing junior engineer, coding new VHDL, debugging multiple PCBs with Virtex-6 LX240T devices on each, interfacing with software development, and supporting government site testing of new hardware, firmware and software. Customer met its milestone and successfully collected necessary data using the new design.

Accepted the task of reviewing and locating bugs in an overdue digital synthesizer design using a 4-lane JESD204B interface comprising a Xilinx DDS core, Xilinx JESD204B TX core (hosted in an Artix XC7A200T-1FFG1156I FPGA), a TI LMK04828 Clock Generator and TI DAC39j84 Quad, 2.8-GSPS Digital to Analog Converter. Re-wrote the startup state machine for initializing the system (not as easy as it sounds) and provided analysis of the entire design for management.

Rescued customer and prevented their loss of a major government contract by quickly assessing the defects in the implementation of their Gigabit Ethernet (1000Base-X) fiber optic link. Proposed and delivered a start-from-scratch implementation of their Data Capture System. Participated in daily stand up meetings while also managing junior engineer, coding new VHDL, debugging multiple PCBs with Virtex-6 LX240T devices on each, interfacing with software development, and supporting government site testing of new hardware, firmware and software. Customer met its milestone and successfully collected necessary data using the new ASPENLOGIC® developed system.

Developed website pages and marketing content to sell Tokyo Electron Device development boards directly to world-wide customers over the internet. Provided phone & email technical support for all products as requested. Delivered outstanding results including the most sales of high end Virtex 6 LX550T development boards in TED history to a single UK customer. Customers appreciated the one stop shop approach.

A new customer needed ASPENLOGIC® to review an existing, well tested Verilog FPGA design (code + specification documents) to determine if adding SystemVerilog (IEEE Std 1800) assertions was necessary. After adding nearly 40 assertions the constrained random OVM simulation showed errors on a number of the assertions.

ASPENLOGIC® integrated three pieces of Xilinx IP to form a stunning data capture and processing engine for its client. 2.5 Gb/s Fiber optic connections between custom, multi-channel ADC/DAC boards and a COTS Avnet evaluation board with a Virtex-5™ SX95T device operating at 250 Mhz delivered high bandwidth connectivity to the proprietary processing engine. The VHDL was designed to replicate a variable number of processing modules and automatically connect them to a variable number of bidirectional Aurora protocol links utilizing SFP optical fiber transceivers. Host software configured each board and received diagnostic information through a register interface accessed via PCI Express.

Drove architecture and implementation of digital logic in the transmit and receive paths of a software defined radio (SDR) for a proprietary continuous phase modulation waveform. Worked w/ Linux driver development specialist to define interface to core logic via a Quicklogic 5064 PCI bus interface IC. Verified, designed and implemented FPGA logic in VHDL for Xilinx Virtex™-4 (170+ Mhz) and Virtex-II devices.

Delivered verilog testplan and testbench for Actel FPGA design. Went beyond scope of original test plan and implemented system level verification that ultimately proved the original design concept could not work thus saving design teams months of difficult board level debug in the lab.

Debugged intractable problem in the gate level implementation of a multi-million gate SOC which the designers spent three months trying to find. I Discovered a flaw in the timing analysis that allowed the design to pass static timing analysis (STA) yet fail in silicon. After examining the pattern of instruction fetch address generation failures, I hypothesized and proved the conjecture that a single hold time violation on one bit of a critical state machine logic path was to blame. Customer verified my suggested modification through E-Beam modification of actual silicon.

Delivered Xilinx Spartan™ IIE FPGA to connect the Vitesse (Sitera) IQ2x000 network processor to a custom SPI-3 interface requiring link and phy interfaces for the receive path. Extensive testing yielded a design without defects that was delivered on-time and months before the customer (Sun Microsystems) needed the device for in-system integration.

Debugged 33 Mhz PCI card containing PLX PCI controller, and Xilinx 4028XL FPGA designed to communicate with a custom silicon optical correlator.

Provided expert consulting to attorneys on an ASIC design contract dispute. Reviewed materials and coached staff on structure of ASICs and their design methodology.

Developed several high speed (65 Mhz) FPGA based, time-sequential color framebuffer controllers for Displaytech Inc.’s ferroelectric liquid crystal (FLC), time sequential color, spatial light modulators. Controllers interfaced to VRAM and SDRAM memory. FPGA designs done with VHDL, Exemplar Logic Leonardo Synthesis software, and Xilinx M1 P&R software. Continued development for customer on next generation FLC Display controller(s).

Delivered hundreds of hours worth of VHDL training courses for Esperan Ltd., an English VHDL training company.

Consulted to Ball Corporation's Real Time Imaging unit on a graphics pipeline ASIC chip set. Established a design methodology which made it possible for the design team to create the chip set in record time. It also lead to a reduction in the size of the largest device by 30% over the previous design. Also designed hardware, directed other consultants in development of floating point hardware, and trained team members in VHDL and Mentor Graphics Autologic synthesis tools.

Consulted to AG Communications Systems in their ASIC design efforts, and trained them in the Mentor Graphics Top-Down design processes. Wrote data pattern generator for testing T1 frame sync operation

Developed and presented seminar at the 1992 VHDL International Users Forum entitled, “VHDL vis-a-vis Top-Down Design”.