Debugged intractable problem in the gate level implementation of a multi-million gate SOC which the designers spent three months trying to find. I Discovered a flaw in the timing analysis that allowed the design to pass static timing analysis (STA) yet fail in silicon. After examining the pattern of instruction fetch address generation failures, I hypothesized and proved the conjecture that a single hold time violation on one bit of a critical state machine logic path was to blame. Customer verified my suggested modification through E-Beam modification of actual silicon.
Consulted to Ball Corporation's Real Time Imaging unit on a graphics pipeline ASIC chip set. Established a design methodology which made it possible for the design team to create the chip set in record time. It also lead to a reduction in the size of the largest device by 30% over the previous design. Also designed hardware, directed other consultants in development of floating point hardware, and trained team members in VHDL and Mentor Graphics Autologic synthesis tools.
Consulted to GE Fanuc Automation in their ASIC design efforts, and trained them in the Mentor Graphics Top-Down design processes.
Consulted to AG Communications Systems in their ASIC design efforts, and trained them in the Mentor Graphics Top-Down design processes. Wrote data pattern generator for testing T1 frame sync operation
Consulted on ASIC designs for an Intel super-computer project requiring a sophisticated, multi-cpu reset initialization controller.