Aspen Logic was called in to replace the lead Senior FPGA architect (who left on early paternity leave) on a VHDL design he created which had not been integrated with key logic components from a third party only eleven days prior to a major demonstration. After spinning up quickly on the FPGA implementation for the demo board's Gen3 ZU48DR Zynq Ultrascale+ RF System On Chip, I entered the lab to assist other RF and Software engineers.
Accepted the task of reviewing and locating bugs for defense contractor in an overdue digital synthesizer design using a 4-lane JESD204B interface comprising a Xilinx DDS core, Xilinx JESD204B TX core (hosted in an Artix XC7A200T-1FFG1156I FPGA), a TI LMK04828 Clock Generator and TI DAC39j84 Quad, 2.8-GSPS Digital to Analog Converter. Re-wrote the startup state machine for initializing the system (not as easy as it sounds) and provided analysis of the entire design for management.
Took over maintenance of both the FPGA Verilog code and the C firmware from two separate engineers. A persistent, but random failure was decreasing calibration yields on the manufacturing line after months of diagnostic effort. In less than a week, my analysis with Chipscope located a supposedly static signal that was pulsing randomly and resetting critical state machines. I traced this to a level translator connected inappropriately to an FPGA I/O pin and devised an FPGA only solution to overcome the problem.
Rescued customer and prevented its loss of a major government contract by quickly assessing the defects in the implementation of its Gigabit Ethernet (1000Base-X) fiber optic link and proposing a start-from-scratch implementation of its Data Capture System. Participated in daily stand up meetings while also managing junior engineer, coding new VHDL, debugging multiple PCBs with Virtex-6 LX240T devices on each, interfacing with software development, and supporting government site testing of new hardware, firmware and software.
The Customer was struggling with a mission critical, embedded design, hosted on a main FPGA board Microblaze soft processor design interfaced with eight daughter cards. A TCP/IP stack provided connectivity to the PC with data collected from eight infrared sensors on each of the daughter cards. The traditional SDK based debugging had run out of steam as months had passed with no viable leads on the cause of a random operational bug. Utilizing Xilinx® Chipscope™, I was able to locate a randomly pulsing signal used in an asyncronous FSM reset.
Rescued customer and prevented their loss of a major government contract by quickly assessing the defects in the implementation of their Gigabit Ethernet (1000Base-X) fiber optic link. Proposed and delivered a start-from-scratch implementation of their Data Capture System. Participated in daily stand up meetings while also managing junior engineer, coding new VHDL, debugging multiple PCBs with Virtex-6 LX240T devices on each, interfacing with software development, and supporting government site testing of new hardware, firmware and software.
Wrote a process for developing project specific FPGA development processes (to meet ISO standards) for a major medical products company.
Designed custom bus implementation to insert master controlled prioritization of data accesses between 16-slave ASICs using Actel ProASICPLUS plus parts.
Delivered verilog testplan and testbench for Actel FPGA design. Went beyond scope of original test plan and implemented system level verification that ultimately proved the original design concept could not work thus saving design teams months of difficult board level debug in the lab.
Worked the design of a special purpose, programmable hardware test engine which utilized three ep20k300efi672 Altera Apex20ke FPGAs. Captured the design in VHDL and synthesized with Leonardo Spectrum and Quartus 2.2 software. Managed the design hierarchy to optimize the re-utilization of logic between the three devices to improve time-to-market. Delivered a synthesizable SDRAM controller, in two weeks, for use between a proprietary message protocol bus and a Micron SDRAM.