ALJ002 - My VARIABLE state of mind
Since 1987 and my first exposure to VHDL, I have seen the humble VARIABLE relegated to the backwaters for use only as combinatorial logic. Verilog coders seem constrained to do the same.
FSM
ALJ003 - WAIT! Describing implicit state machines with VHDL
The VHDL PROCESS, written with multiple WAIT statements, provides a powerful way to develop implicit state machines (ISM). The ISM lacks an explicit state variable to track the current state thus making it easy and quick to add, delete or modify states with simple text edit commands.