ASPENLOGIC® offers professional services to support your company's effort to produce high quality FPGA logic designs.

Janitorial Engineering (post development)

  • Debug
  • Feature addition(s)
  • Documentation

Proposal Development

  • High level architectural alternatives exploration
  • Initial system partition
  • Initial rough, FPGA logic block diagrams
  • Initial Rough Order of Magitude (ROM) schedule estimate
  • Cost development estimates

Logic verification

  • Test plan documenation
  • Requirements tracking
  • Behavioral HDL testbench coding
  • SystemVerilog assertions development
  • System simulation
  • Gate level simulation w/ back annotated timing
  • Unit (block level) test development
  • Regression testing environment construction


  • System architecture
  • Preliminary Design Reviews (PDR)
  • Clock domain crossing analysis
  • System reset engineering
  • Clocking domains configuration and reset integration
  • External electrical interface engineering


  • SOC FPGA device and peripherals selection/configuration
  • HDL Coding
    • Synthesizable and behavioral level VHDL coding
    • Synthesizable Verilog (or SystemVerilog) HDL coding
    • HDL Code reviews
  • I/O Pin placement and configuration
  • Vendor tool scripting using TCL, Rake, Make
  • Vendor tool configuration
  • Build to bitstream of your HDL designs
  • Timing Closure


  • Single or multi-FPGA
  • Embedded C plus custom hardware
  • In-system debugging using FPGA vendor internal logic analyzer capability


  • 1-5 day customized VHDL language immersion

Legal Team

  • Expert Consulting in patent litigation matters


  • Configuration management version control and tracking
  • Source code control with Subversion or Git
  • Crisis intervention for difficult designs or to reign in schedules due to lost employees