ALJ002 - My VARIABLE state of mind

Since 1987 and my first exposure to VHDL, I have seen the humble VARIABLE relegated to the backwaters for use only as combinatorial logic. Verilog coders seem constrained to do the same. ALJ002 presents a convention for using blocking assignments effectively with locally declared REG objects in Verilog and variables in VHDL. It specifically addresses the case for inferring flip-flops and why it also eliminates the possibility of execution order dependent code.