ALJ003 - WAIT! Describing implicit state machines with VHDL

The VHDL PROCESS, written with multiple WAIT statements, provides a powerful way to develop implicit state machines (ISM). The ISM lacks an explicit state variable to track the current state thus making it easy and quick to add, delete or modify states with simple text edit commands. In ALJ003, synthesizable and behavioral state machine styles are covered with examples and suggestions for efficient application of this technique.