Took Over Maintenance of Existing C and Verilog Code Base

Took over maintenance of both the FPGA Verilog code and the C firmware from two separate engineers. A persistent, but random failure was decreasing calibration yields on the manufacturing line after months of diagnostic effort. In less than a week, my analysis with Chipscope located a supposedly static signal that was pulsing randomly and resetting critical state machines. I traced this to a level translator connected inappropriately to an FPGA I/O pin and devised an FPGA only solution to overcome the problem. Over the course of four major releases, ASPENLOGIC® crafted a brand new VoSPI interface to communicate with next generation Lepton Infrared cameras, ported the TCP/IP firmware from the open source LwIP stack to the commercial Treck stack, and fixed numerous other bugs.