Create Smoke Tests for PCIe Interface to HLS Logic

Wrote design side SystemVerilog smoke tests for PCIe interface to HLS logic for Tier 1 Aerospace Agile Cyber Engineering team using Xilinx AXI4/AXI4 Stream Verification IP (VIP) on a project demanding DO-254 level controls. Provided expertise in design requirement analysis; led RTL design reviews; coached team mates on documentation development and RTL coding styles/standards. Authored technical contract deliverable specification documents and co-authored SOW for the design’s outsourced UVM verification effort. Educated contract winner’s technical staff on the design and provided guidance/ analysis through Critical Design Review.