Architected Custom IEEE 802.1Q Bridge

Took the responsibility for developing the system architecture for a custom 802.1Q bridge with customized 10GBASE-KR links operating with proprietary protocols to/from external ASICs. Wrote hardware design documentation and software interface documents including block diagrams and timing diagrams using MS Visio. Led technical interchange meetings with my customer’s customer to uncover and understand unstated FPGA requirements. Coded a highly programmable Time Division Multiplexing (TDM) scheduling back end with weighted fair queuing (WFQ), HDLC encoding, frame buffering, realignment engine and register interface in SystemVerilog. Coordinated verification with UVM development team. Operated remotely (COVID-19) for entire project and for a significant stretch without the FPGA lead who was out on paternity leave.