Aspen Logic was called in to replace the lead Senior FPGA architect (who left on early paternity leave) on a VHDL design he created which had not been integrated with key logic components from a third party only eleven days prior to a major demonstration. After spinning up quickly on the FPGA implementation for the demo board's Gen3 ZU48DR Zynq Ultrascale+ RF System On Chip, I entered the lab to assist other RF and Software engineers. We worked madly to get demonstration hardware running on the RF FPGA development board using the third party's new and untested IP that frequently changed daily. I coordinated the efforts of the third party engineers, integrated their outputs into the main design and ran builds that sometimes failed to meet timing or even fit in the part! The whole team operated without any contact with the Sr FPGA Architect who was completely out of contact. I regularly briefed the project director on status and provided guidance on suggested integration approaches as bugs appeared with serious potential for derailing the critical demonstration. The result was a successful demonstration of the hardware.