Custom Bus Implementation and Analysis
Designed custom bus implementation to insert master controlled prioritization of data accesses between 16-slave ASICs using Actel ProASICPLUS plus parts.
Actel
Verilog Test Plan and Testbench
Delivered verilog testplan and testbench for Actel FPGA design. Went beyond scope of original test plan and implemented system level verification that ultimately proved the original design concept could not work thus saving design teams months of difficult board level debug in the lab.