Custom Bus Implementation and Analysis

AspenLogic — Sun, 04 Mar 2018 00:18:48 +0000

Designed custom bus implementation to insert master controlled prioritization of data accesses between 16-slave ASICs using Actel ProASICPLUS plus parts.

Verilog Test Plan and Testbench

AspenLogic — Sun, 04 Mar 2018 00:17:36 +0000

Delivered verilog testplan and testbench for Actel FPGA design. Went beyond scope of original test plan and implemented system level verification that ultimately proved the original design concept could not work thus saving design teams months of difficult board level debug in the lab.