https://aspenlogic.com/drupal7/taxonomy/term/132/all en https://aspenlogic.com/drupal7/node/50 <div class="field field-name-body field-type-text-with-summary field-label-hidden"><div class="field-items"><div class="field-item even" property="content:encoded"><p>Worked the design of a special purpose, programmable hardware test engine which utilized three ep20k300efi672 Altera Apex20ke FPGAs. Captured the design in VHDL and synthesized with Leonardo Spectrum and Quartus 2.2 software. Managed the design hierarchy to optimize the re-utilization of logic between the three devices to improve time-to-market. Delivered a synthesizable SDRAM controller, in two weeks, for use between a proprietary message protocol bus and a Micron SDRAM.</p> </div></div></div> Sun, 04 Mar 2018 00:10:49 +0000 AspenLogic 50 at https://aspenlogic.com/drupal7