Debugged Multi-Million gate SOC ASIC to Save Project From Failure

Debugged intractable problem in the gate level implementation of a multi-million gate SOC which the designers spent three months trying to find. I Discovered a flaw in the timing analysis that allowed the design to pass static timing analysis (STA) yet fail in silicon. After examining the pattern of instruction fetch address generation failures, I hypothesized and proved the conjecture that a single hold time violation on one bit of a critical state machine logic path was to blame. Customer verified my suggested modification through E-Beam modification of actual silicon.