Wrote design side SystemVerilog smoke tests for PCIe interface to HLS logic for Tier 1 Aerospace Agile Cyber Engineering team using Xilinx AXI4/AXI4 Stream Verification IP (VIP) on a project demanding DO-254 level controls. Provided expertise in design requirement analysis; led RTL design reviews; coached team mates on documentation development and RTL coding styles/standards. Authored technical contract deliverable specification documents and co-authored SOW for the design’s outsourced UVM verification effort.
ASPENLOGIC® integrated three pieces of Xilinx IP to form a stunning data capture and processing engine for its client. 2.5 Gb/s Fiber optic connections between custom, multi-channel ADC/DAC boards and a COTS Avnet evaluation board with a Virtex-5™ SX95T device operating at 250 Mhz delivered high bandwidth connectivity to the proprietary processing engine. The VHDL was designed to replicate a variable number of processing modules and automatically connect them to a variable number of bidirectional Aurora protocol links utilizing SFP optical fiber transceivers.