Augmented OVM Test with System Verilog Assertions

AspenLogic — Sun, 04 Mar 2018 00:27:09 +0000

A new customer needed ASPENLOGIC® to review an existing, well tested Verilog FPGA design (code + specification documents) to determine if adding SystemVerilog (IEEE Std 1800) assertions was necessary. After adding nearly 40 assertions the constrained random OVM simulation showed errors on a number of the assertions.

SystemVerilog Assertions

Augmented OVM Test with System Verilog Assertions