UVM https://aspenlogic.com/drupal7/taxonomy/term/182/all en Create Smoke Tests for PCIe Interface to HLS Logic https://aspenlogic.com/drupal7/node/71 <div class="field field-name-body field-type-text-with-summary field-label-hidden"><div class="field-items"><div class="field-item even" property="content:encoded"><p>Wrote design side SystemVerilog smoke tests for PCIe interface to HLS logic for Tier 1 Aerospace Agile Cyber Engineering team using Xilinx AXI4/AXI4 Stream Verification IP (VIP) on a project demanding DO-254 level controls. Provided expertise in design requirement analysis; led RTL design reviews; coached team mates on documentation development and RTL coding styles/standards. Authored technical contract deliverable specification documents and co-authored SOW for the design’s outsourced UVM verification effort.</p></div></div></div> Thu, 07 Oct 2021 23:23:40 +0000 AspenLogic 71 at https://aspenlogic.com/drupal7