Took the responsibility for developing the system architecture for a custom 802.1Q bridge with customized 10GBASE-KR links operating with proprietary protocols to/from external ASICs. Wrote hardware design documentation and software interface documents including block diagrams and timing diagrams using MS Visio. Led technical interchange meetings with my customer’s customer to uncover and understand unstated FPGA requirements.
Wrote design side SystemVerilog smoke tests for PCIe interface to HLS logic for Tier 1 Aerospace Agile Cyber Engineering team using Xilinx AXI4/AXI4 Stream Verification IP (VIP) on a project demanding DO-254 level controls. Provided expertise in design requirement analysis; led RTL design reviews; coached team mates on documentation development and RTL coding styles/standards. Authored technical contract deliverable specification documents and co-authored SOW for the design’s outsourced UVM verification effort.
