Last Minute Replacement for Engineer

AspenLogic — Thu, 07 Oct 2021 23:41:50 +0000

Aspen Logic was called in to replace the lead Senior FPGA architect (who left on early paternity leave) on a VHDL design he created which had not been integrated with key logic components from a third party only eleven days prior to a major demonstration. After spinning up quickly on the FPGA implementation for the demo board's Gen3 ZU48DR Zynq Ultrascale+ RF System On Chip, I entered the lab to assist other RF and Software engineers.