FPGA

Last Minute Replacement for Engineer

AspenLogic — Thu, 07 Oct 2021 23:41:50 +0000

Aspen Logic was called in to replace the lead Senior FPGA architect (who left on early paternity leave) on a VHDL design he created which had not been integrated with key logic components from a third party only eleven days prior to a major demonstration. After spinning up quickly on the FPGA implementation for the demo board's Gen3 ZU48DR Zynq Ultrascale+ RF System On Chip, I entered the lab to assist other RF and Software engineers.

Review and Locate Bugs in 4-lane JESD204B Interface Design

AspenLogic — Thu, 07 Oct 2021 23:21:58 +0000

Accepted the task of reviewing and locating bugs for defense contractor in an overdue digital synthesizer design using a 4-lane JESD204B interface comprising a Xilinx DDS core, Xilinx JESD204B TX core (hosted in an Artix XC7A200T-1FFG1156I FPGA), a TI LMK04828 Clock Generator and TI DAC39j84 Quad, 2.8-GSPS Digital to Analog Converter. Re-wrote the startup state machine for initializing the system (not as easy as it sounds) and provided analysis of the entire design for management.

Took Over Maintenance of Existing C and Verilog Code Base

AspenLogic — Thu, 07 Oct 2021 23:19:25 +0000

Took over maintenance of both the FPGA Verilog code and the C firmware from two separate engineers. A persistent, but random failure was decreasing calibration yields on the manufacturing line after months of diagnostic effort. In less than a week, my analysis with Chipscope located a supposedly static signal that was pulsing randomly and resetting critical state machines. I traced this to a level translator connected inappropriately to an FPGA I/O pin and devised an FPGA only solution to overcome the problem.

Rescued Customer from Failing Giabit Ethernet Fiber Optic Link Design

AspenLogic — Thu, 07 Oct 2021 23:16:38 +0000

Rescued customer and prevented its loss of a major government contract by quickly assessing the defects in the implementation of its Gigabit Ethernet (1000Base-X) fiber optic link and proposing a start-from-scratch implementation of its Data Capture System. Participated in daily stand up meetings while also managing junior engineer, coding new VHDL, debugging multiple PCBs with Virtex-6 LX240T devices on each, interfacing with software development, and supporting government site testing of new hardware, firmware and software.

Multi-FPGA Embedded System Debug

AspenLogic — Sun, 04 Mar 2018 00:40:10 +0000

The Customer was struggling with a mission critical, embedded design, hosted on a main FPGA board Microblaze soft processor design interfaced with eight daughter cards. A TCP/IP stack provided connectivity to the PC with data collected from eight infrared sensors on each of the daughter cards. The traditional SDK based debugging had run out of steam as months had passed with no viable leads on the cause of a random operational bug. Utilizing Xilinx® Chipscope™, I was able to locate a randomly pulsing signal used in an asyncronous FSM reset.

1000Base-X GigE Fiber Link Project Rescue

AspenLogic — Sun, 04 Mar 2018 00:37:47 +0000

Rescued customer and prevented their loss of a major government contract by quickly assessing the defects in the implementation of their Gigabit Ethernet (1000Base-X) fiber optic link. Proposed and delivered a start-from-scratch implementation of their Data Capture System. Participated in daily stand up meetings while also managing junior engineer, coding new VHDL, debugging multiple PCBs with Virtex-6 LX240T devices on each, interfacing with software development, and supporting government site testing of new hardware, firmware and software.

Medical Device FPGA Development Process

AspenLogic — Sun, 04 Mar 2018 00:28:07 +0000

Wrote a process for developing project specific FPGA development processes (to meet ISO standards) for a major medical products company.

Custom Bus Implementation and Analysis

AspenLogic — Sun, 04 Mar 2018 00:18:48 +0000

Designed custom bus implementation to insert master controlled prioritization of data accesses between 16-slave ASICs using Actel ProASICPLUS plus parts.

Verilog Test Plan and Testbench

AspenLogic — Sun, 04 Mar 2018 00:17:36 +0000

Delivered verilog testplan and testbench for Actel FPGA design. Went beyond scope of original test plan and implemented system level verification that ultimately proved the original design concept could not work thus saving design teams months of difficult board level debug in the lab.

Programmable Hardware Test Engine

AspenLogic — Sun, 04 Mar 2018 00:10:49 +0000

Worked the design of a special purpose, programmable hardware test engine which utilized three ep20k300efi672 Altera Apex20ke FPGAs. Captured the design in VHDL and synthesized with Leonardo Spectrum and Quartus 2.2 software. Managed the design hierarchy to optimize the re-utilization of logic between the three devices to improve time-to-market. Delivered a synthesizable SDRAM controller, in two weeks, for use between a proprietary message protocol bus and a Micron SDRAM.

The Transistor Effect

Tim Davis — Fri, 02 Mar 2018 05:20:18 +0000

Who knew that transistors would have such a transformative power over our daily lives? We carry billions of them around in our pocket, on our wrist, in our computers. They are ubiquitous but also invisible.

Bugs? Not in my schedule please.

Tim Davis — Fri, 24 Feb 2017 17:44:00 +0000

I have rescued a few designs during my 25+ years at the helm of Aspen Logic's FPGA/ASIC contracting business. Reasons abound for the causes of the failures but there are three areas that need consistent focus:

Designers give little up front thought to logic reset which leads to insidious, hard to find bugs
Management typically assigns a cost of $0 to bugs because FPGA devices are re-programmable so no time is allocated in the schedule for squishing them
Lack of a road map for features and fixes which makes decision making on large design efforts difficult

ALJ001 - Managing synchronizer MTBF

AspenLogic — Wed, 25 Feb 2009 18:18:06 +0000