Verilog Test Plan and Testbench

AspenLogic — Sun, 04 Mar 2018 00:17:36 +0000

Delivered verilog testplan and testbench for Actel FPGA design. Went beyond scope of original test plan and implemented system level verification that ultimately proved the original design concept could not work thus saving design teams months of difficult board level debug in the lab.

Verifying Validation and Validating Verification

Tim Davis — Fri, 22 Oct 2010 04:22:00 +0000

People (I guess we classify engineers as people) have always talked about verification and the "testing" of a piece of hardware to see if it works as the "same thing". Unfortunately for us there is a movement within international standards bodies (dating back centuries) to have us believe that there are really two types of testing: verification and validation.

Is your head spinning?