https://aspenlogic.com/drupal7/taxonomy/term/4/all en https://aspenlogic.com/drupal7/node/16 <div class="field field-name-body field-type-text-with-summary field-label-hidden"><div class="field-items"><div class="field-item even" property="content:encoded"><hr /> <p>I<img alt="" src="/drupal7/sites/default/files/default_images/aspenlogic_red_or_logic_gate_86x72.png" style="float:left; height:72px; width:86px; margin:10px 10px 10px 10px" /> have rescued a few designs during my 25+ years at the helm of Aspen Logic's FPGA/ASIC contracting business. Reasons abound for the causes of the failures but there are three areas that need consistent focus:</p> <ol> <li>Designers give little up front thought to logic reset which leads to insidious, hard to find bugs</li> <li>Management typically assigns a cost of $0 to bugs because FPGA devices are re-programmable so no time is allocated in the schedule for squishing them</li> <li>Lack of a road map for features and fixes which makes decision making on large design efforts difficult</li> </ol> <p></div></div></div> Fri, 24 Feb 2017 17:44:00 +0000 Tim Davis 16 at https://aspenlogic.com/drupal7