Aspen Logic was called in to replace the lead Senior FPGA architect (who left on early paternity leave) on a VHDL design he created which had not been integrated with key logic components from a third party only eleven days prior to a major demonstration. After spinning up quickly on the FPGA implementation for the demo board's Gen3 ZU48DR Zynq Ultrascale+ RF System On Chip, I entered the lab to assist other RF and Software engineers.
Designed, implemented and simulated the VHDL design for a custom 1024 channel DAC controller (via 256 DACs) that required broadcast capability in addition to programmable FIFO read access for maximum throughput to the total array of DACs. The SPI bridge was developed to permit parallel access in groups of 64 channels as needed by the system processor.
Rescued customer and prevented their loss of a major government contract by quickly assessing the defects in the implementation of their Gigabit Ethernet (1000Base-X) fiber optic link. Proposed and delivered a start-from-scratch implementation of their Data Capture System. Participated in daily stand up meetings while also managing junior engineer, coding new VHDL, debugging multiple PCBs with Virtex-6 LX240T devices on each, interfacing with software development, and supporting government site testing of new hardware, firmware and software.
Developed an 80 MHz Cameralink dual medium interface for the Xenics Cheetah-640CL which was the world's fastest IR camera. This project also required the design of VHDL interface code for talking with peripherals connected to a TB-6V-LX550T-PCIEXP. It communicated using the Xilinx Aurora protocol over two sets of four 3.125 Gbps fiber optic links to Virtex-6 SX475T and SX315T populated XMC cards. Co-designed the architecture and VHDL implementation strategy for the entire system.
ASPENLOGIC® integrated three pieces of Xilinx IP to form a stunning data capture and processing engine for its client. 2.5 Gb/s Fiber optic connections between custom, multi-channel ADC/DAC boards and a COTS Avnet evaluation board with a Virtex-5™ SX95T device operating at 250 Mhz delivered high bandwidth connectivity to the proprietary processing engine. The VHDL was designed to replicate a variable number of processing modules and automatically connect them to a variable number of bidirectional Aurora protocol links utilizing SFP optical fiber transceivers.
Drove architecture and implementation of digital logic in the transmit and receive paths of a software defined radio (SDR) for a proprietary continuous phase modulation waveform. Worked w/ Linux driver development specialist to define interface to core logic via a Quicklogic 5064 PCI bus interface IC. Verified, designed and implemented FPGA logic in VHDL for Xilinx Virtex™-4 (170+ Mhz) and Virtex-II devices.
Delivered hundreds of hours worth of VHDL training courses for Esperan Ltd., an English VHDL training company.
Performed scheduling and management of a two-week project to design and simulate control logic for a client with a hard, ASIC, fab deadline in order to replace uncompleted work by another vendor. Extracted design requirements from customer specification and developed test plan to guide verification effort. Supervised partners in VHDL design and simulation to meet goals and performed design synthesis using Veribest Inc.'s synthesis software.
Consulted to Ball Corporation's Real Time Imaging unit on a graphics pipeline ASIC chip set. Established a design methodology which made it possible for the design team to create the chip set in record time. It also lead to a reduction in the size of the largest device by 30% over the previous design. Also designed hardware, directed other consultants in development of floating point hardware, and trained team members in VHDL and Mentor Graphics Autologic synthesis tools.
Consulted on ASIC designs for an Intel super-computer project requiring a sophisticated, multi-cpu reset initialization controller.