Took over maintenance of both the FPGA Verilog code and the C firmware from two separate engineers. A persistent, but random failure was decreasing calibration yields on the manufacturing line after months of diagnostic effort. In less than a week, my analysis with Chipscope located a supposedly static signal that was pulsing randomly and resetting critical state machines. I traced this to a level translator connected inappropriately to an FPGA I/O pin and devised an FPGA only solution to overcome the problem.
The Customer was struggling with a mission critical, embedded design, hosted on a main FPGA board Microblaze soft processor design interfaced with eight daughter cards. A TCP/IP stack provided connectivity to the PC with data collected from eight infrared sensors on each of the daughter cards. The traditional SDK based debugging had run out of steam as months had passed with no viable leads on the cause of a random operational bug. Utilizing Xilinx® Chipscope™, I was able to locate a randomly pulsing signal used in an asyncronous FSM reset.
Delivered verilog testplan and testbench for Actel FPGA design. Went beyond scope of original test plan and implemented system level verification that ultimately proved the original design concept could not work thus saving design teams months of difficult board level debug in the lab.