ALJ002 - My VARIABLE state of mind
Since 1987 and my first exposure to VHDL, I have seen the humble VARIABLE relegated to the backwaters for use only as combinatorial logic. Verilog coders seem constrained to do the same.
Since 1987 and my first exposure to VHDL, I have seen the humble VARIABLE relegated to the backwaters for use only as combinatorial logic. Verilog coders seem constrained to do the same.