ASIC Design Crisis Intervention

AspenLogic — Sat, 03 Mar 2018 20:14:01 +0000

Performed scheduling and management of a two-week project to design and simulate control logic for a client with a hard, ASIC, fab deadline in order to replace uncompleted work by another vendor. Extracted design requirements from customer specification and developed test plan to guide verification effort. Supervised partners in VHDL design and simulation to meet goals and performed design synthesis using Veribest Inc.'s synthesis software.