Debug

Multi-FPGA Embedded System Debug

The Customer was struggling with a mission critical, embedded design, hosted on a main FPGA board Microblaze soft processor design interfaced with eight daughter cards. A TCP/IP stack provided connectivity to the PC with data collected from eight infrared sensors on each of the daughter cards. The traditional SDK based debugging had run out of steam as months had passed with no viable leads on the cause of a random operational bug. Utilizing Xilinx® Chipscope™, I was able to locate a randomly pulsing signal used in an asyncronous FSM reset.

Debugged Multi-Million gate SOC ASIC to Save Project From Failure

Debugged intractable problem in the gate level implementation of a multi-million gate SOC which the designers spent three months trying to find. I Discovered a flaw in the timing analysis that allowed the design to pass static timing analysis (STA) yet fail in silicon. After examining the pattern of instruction fetch address generation failures, I hypothesized and proved the conjecture that a single hold time violation on one bit of a critical state machine logic path was to blame. Customer verified my suggested modification through E-Beam modification of actual silicon.

Analog SLM PCI Card Debug

Delivered crisis intervention support on a late project for a PCI card design. The system did not send correctly formatted data to the analog spatial light modulator (SLM). Re-architecting the design yielded a functional platform for testing of the SLM.

Short Notice Engineering Replacement

Stepped in on few days notice to replace an engineer at client site. Found and fixed over 20 bugs in engineer’s ECC softcore controller design -- several were show stoppers. Brought design back to Colorado to complete simulation against test plan I developed. Work on other client projects required rapid acquisition of knowledge about error control coding mathematics to complete modifications to Perl scripts, which programmed the creation of schematics in Design Architect.

Bugs? Not in my schedule please.

I have rescued a few designs during my 25+ years at the helm of Aspen Logic's FPGA/ASIC contracting business. Reasons abound for the causes of the failures but there are three areas that need consistent focus:

Designers give little up front thought to logic reset which leads to insidious, hard to find bugs
Management typically assigns a cost of $0 to bugs because FPGA devices are re-programmable so no time is allocated in the schedule for squishing them
Lack of a road map for features and fixes which makes decision making on large design efforts difficult