Programmable Hardware Test Engine

Worked the design of a special purpose, programmable hardware test engine which utilized three ep20k300efi672 Altera Apex20ke FPGAs. Captured the design in VHDL and synthesized with Leonardo Spectrum and Quartus 2.2 software. Managed the design hierarchy to optimize the re-utilization of logic between the three devices to improve time-to-market. Delivered a synthesizable SDRAM controller, in two weeks, for use between a proprietary message protocol bus and a Micron SDRAM.

Displaytech FLC SLM Controller

Developed several high speed (65 Mhz) FPGA based, time-sequential color framebuffer controllers for Displaytech Inc.’s ferroelectric liquid crystal (FLC), time sequential color, spatial light modulators. Controllers interfaced to VRAM and SDRAM memory. FPGA designs done with VHDL, Exemplar Logic Leonardo Synthesis software, and Xilinx M1 P&R software. Continued development for customer on next generation FLC Display controller(s).