Aspen Logic was called in to replace the lead Senior FPGA architect (who left on early paternity leave) on a VHDL design he created which had not been integrated with key logic components from a third party only eleven days prior to a major demonstration. After spinning up quickly on the FPGA implementation for the demo board's Gen3 ZU48DR Zynq Ultrascale+ RF System On Chip, I entered the lab to assist other RF and Software engineers.
Wrote design side SystemVerilog smoke tests for PCIe interface to HLS logic for Tier 1 Aerospace Agile Cyber Engineering team using Xilinx AXI4/AXI4 Stream Verification IP (VIP) on a project demanding DO-254 level controls. Provided expertise in design requirement analysis; led RTL design reviews; coached team mates on documentation development and RTL coding styles/standards. Authored technical contract deliverable specification documents and co-authored SOW for the design’s outsourced UVM verification effort.
Accepted the task of reviewing and locating bugs for defense contractor in an overdue digital synthesizer design using a 4-lane JESD204B interface comprising a Xilinx DDS core, Xilinx JESD204B TX core (hosted in an Artix XC7A200T-1FFG1156I FPGA), a TI LMK04828 Clock Generator and TI DAC39j84 Quad, 2.8-GSPS Digital to Analog Converter. Re-wrote the startup state machine for initializing the system (not as easy as it sounds) and provided analysis of the entire design for management.